ADDI7100BCPZ datasheet(15/20 Pages) AD

15 / 20 page

ADDI7100

Rev. C | Page 15 of 20

INITIAL POWER-ON SEQUENCE

After power-on, the ADDI7100 automatically resets all internal

registers to default values. Settling of the internal voltage refer-

ence takes approximately 1 ms to complete. During this time,

normal clock signals and serial write operations can take place,

but valid output data do not occur until the reference is fully

settled. When loading the desired register settings, the STARTUP

GROUNDING AND DECOUPLING

RECOMMENDATIONS

As shown in Figure 15, a single ground plane is recommended

for the ADDI7100. This ground plane should be as continuous

as possible to ensure that all analog decoupling capacitors

provide the lowest possible impedance path between the power

and bypass pins and their respective ground pins. Place all

decoupling capacitors as close as possible to the package pins.

A single clean power supply is recommended for the ADDI7100,

but a separate digital driver supply can be used for DRVDD

(Pin 11). Always decouple DRVDD to DRVSS (Pin 12), which

should be connected to the analog ground plane. The advantages

of using a separate digital driver supply include using a lower

voltage (2.7 V) to match levels with a 2.7 V ASIC, and reducing

digital power dissipation and potential noise coupling. If the

digital outputs must drive a load larger than 20 pF, buffering is

the recommended method to reduce digital code transition

noise. Alternatively, placing series resistors close to the digital

output pins may also help to reduce noise.

Note that the exposed pad on the bottom of the package should

be soldered to the ground plane of the printed circuit board.

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