AD7863ARS-10REEL datasheet(11/24 Pages) AD

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AD7863

Rev. B | Page 11 of 24

Gain error can be adjusted at either the first code transition (ADC

negative full scale) or the last code transition (ADC positive full

scale). The trim procedures for both cases are as follows:

Positive Full-Scale Adjust (−10 Version)

Apply a voltage of 9.9927 V (FS/2 – 1 LSBs) at V1. Adjust R2

until the ADC output code flickers between 01 1111 1111 1110

and 01 1111 1111 1111.

Negative Full-Scale Adjust (−10 Version)

Apply a voltage of −9.9976 V (−FS + 1 LSB) at V1. Adjust R2

until the ADC output code flickers between 10 0000 0000 0000

and 10 0000 0000 0001.

An alternative scheme for adjusting full-scale error in systems

that use an external reference is to adjust the voltage at the VREF

pin until the full-scale error for any of the channels is adjusted

out. The good full-scale matching of the channels ensures small

full-scale errors on the other channels.

TIMING AND CONTROL

Figure 7 shows the timing and control sequence required to

obtain optimum performance (Mode 1) from the AD7863. In

the sequence shown, a conversion is initiated on the falling edge

of CONVST. This places both track-and-holds into hold

simultaneously and new data from this conversion is available

in the output register of the AD7863 5.2 μs later. The BUSY

signal indicates the end of conversion and at this time the

conversion results for both channels are available to be read. A

second conversion is then initiated. If the multiplexer select (A0)

is low, the first and second read pulses after the first conversion

accesses the result from Channel A (VA1 and VA2, respectively).

The third and fourth read pulses, after the second conversion

and A0 high, accesses the result from Channel B (VB1 and VB2,

respectively). The state of A0 can be changed any time after the

CONVST goes high, that is, track-and-holds into hold and 500 ns

prior to the next falling edge of CONVST. Note that A0 should

not be changed during conversion if the nonselected channels

have negative voltages applied to them, which are outside the

input range of the AD7863, because this affects the conversion

in progress. Data is read from the part via a 14-bit parallel data

bus with standard CS and RD signal, that is, the read operation

consists of a negative going pulse on the CS pin combined with

two negative going pulses on the RD pin (while the CS is low),

accessing the two 14-bit results. Once the read operation has

taken place, a further 400 ns should be allowed before the next

falling edge of CONVST to optimize the settling of the track-

and-hold amplifier before the next conversion is initiated.

The achievable throughput rate for the part is 5.2 μs (conversion

time) plus 100 ns (read time) plus 0.4 μs (quiet time). This

results in a minimum throughput time of 5.7 μs (equivalent to

a throughput rate of 175 kHz).

VA1

VA2

VB1

VB2

CONVST

BUSY

DATA

tCONV = 5.2µs

tACQ

Figure 7. Mode 1 Timing Operation Diagram for High Sampling Performance

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