AD7899 datasheet(4/16 Pages) AD

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REV. A

AD7899

–4–

TIMING CHARACTERISTICS1, 2

A, B and S

Parameter

Versions

Unit

Test Conditions/Comments

tCONV

2.2

µs max

Conversion Time, Internal Clock

2.46

µs max

CLKIN = 6.5 MHz

tACQ

0.3

µs max

Acquisition Time

tEOC

120

ns min

EOC Pulsewidth

180

ns max

tWAKE-UP – External VREF

µs max

STBY Rising Edge to CONVST Rising Edge

(See Standby Mode Operation)

ns min

CONVST Pulsewidth

ns min

CONVST Rising Edge to BUSY Rising Edge

Read Operation

ns min

CS to RD Setup Time

ns min

CS to RD Hold Time

ns min

Read Pulsewidth

ns max

Data Access Time after Falling Edge of

RD, V

DRIVE = 5 V

ns max

Data Access Time after Falling Edge of

RD, V

DRIVE = 3 V

ns min

Bus Relinquish Time after Rising Edge of

ns max

ns min

BUSY Falling Edge to

RD Delay

External Clock

ns min

CLKIN to

CONVST Rising Edge Setup Time

t10

ns min

CLKIN to

CONVST Rising Edge Hold Time

t11

100

ns min

CONVST Rising Edge to CLK Falling Edge

NOTES

1 Sample tested at 25

°C to ensure compliance. All input signals are measured with tr = tf = 1 ns (10% to 90% of V

DRIVE) and timed from a voltage level of V DRIVE/2.

2 See Figures 5, 6, 7, and 8.

3 Measured with the load circuit of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.0 V.

4These times are derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then

extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus

relinquish times of the part and as such are independent of external bus loading capacitances.

5 Refer to the Standby Mode Operation section.

Specifications subject to change without notice.

(VDD = 5 V

5%, AGND = DGND = 0 V, VREF = Internal, Clock = Internal; All specifications TMIN

to TMAX and valid for VDRIVE = 3 V

5% and 5 V

5% unless otherwise noted.)

1.6mA

1.6V

400 A

50pF

OUTPUT

Figure 1. Load Circuit for Access Time and Bus Relinquish Time

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