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PIC18F2525IP bảng dữ liệu(PDF) 54 Page - Microchip Technology |
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PIC18F2525IP bảng dữ liệu(HTML) 54 Page - Microchip Technology |
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54 / 412 page  PIC18F2525/2620/4525/4620 DS39626E-page 52 © 2008 Microchip Technology Inc. IPR2 2525 2620 4525 4620 11-1 1111 11-1 1111 uu-u uuuu PIR2 2525 2620 4525 4620 00-0 0000 00-0 0000 uu-u uuuu(1) PIE2 2525 2620 4525 4620 00-0 0000 00-0 0000 uu-u uuuu IPR1 2525 2620 4525 4620 1111 1111 1111 1111 uuuu uuuu 2525 2620 4525 4620 -111 1111 -111 1111 -uuu uuuu PIR1 2525 2620 4525 4620 0000 0000 0000 0000 uuuu uuuu(1) 2525 2620 4525 4620 -000 0000 -000 0000 -uuu uuuu(1) PIE1 2525 2620 4525 4620 0000 0000 0000 0000 uuuu uuuu 2525 2620 4525 4620 -000 0000 -000 0000 -uuu uuuu OSCTUNE 2525 2620 4525 4620 00-0 0000 00-0 0000 uu-u uuuu TRISE 2525 2620 4525 4620 0000 -111 0000 -111 uuuu -uuu TRISD 2525 2620 4525 4620 1111 1111 1111 1111 uuuu uuuu TRISC 2525 2620 4525 4620 1111 1111 1111 1111 uuuu uuuu TRISB 2525 2620 4525 4620 1111 1111 1111 1111 uuuu uuuu TRISA(5) 2525 2620 4525 4620 1111 1111(5) 1111 1111(5) uuuu uuuu(5) LATE 2525 2620 4525 4620 ---- -xxx ---- -uuu ---- -uuu LATD 2525 2620 4525 4620 xxxx xxxx uuuu uuuu uuuu uuuu LATC 2525 2620 4525 4620 xxxx xxxx uuuu uuuu uuuu uuuu LATB 2525 2620 4525 4620 xxxx xxxx uuuu uuuu uuuu uuuu LATA(5) 2525 2620 4525 4620 xxxx xxxx(5) uuuu uuuu(5) uuuu uuuu(5) PORTE 2525 2620 4525 4620 ---- xxxx ---- uuuu ---- uuuu 2525 2620 4525 4620 ---- x--- ---- u--- ---- u--- PORTD 2525 2620 4525 4620 xxxx xxxx uuuu uuuu uuuu uuuu PORTC 2525 2620 4525 4620 xxxx xxxx uuuu uuuu uuuu uuuu PORTB 2525 2620 4525 4620 xxxx xxxx uuuu uuuu uuuu uuuu PORTA(5) 2525 2620 4525 4620 xx0x 0000(5) uu0u 0000(5) uuuu uuuu(5) TABLE 4-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Register Applicable Devices Power-on Reset, Brown-out Reset MCLR Resets, WDT Reset, RESET Instruction, Stack Resets Wake-up via WDT or Interrupt Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 4: See Table 4-3 for Reset value for specific condition. 5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read ‘0’. |
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