AD7980-EP

Rev. 0 | Page 5 of 12

TIMING SPECIFICATIONS

−55°C to +125°C, VDD = 2.37 V to 2.63 V, VIO = 3.3 V to 5.5 V, unless otherwise stated. See Figure 2 and Figure 3 for load conditions.

Table 4.

Parameter

Symbol

Min

Typ

Max

Unit

Conversion Time: CNV Rising Edge to Data Available

t

CONV

500

710

ns

Acquisition Time

t

ACQ

290

ns

Time Between Conversions

t

CYC

1000

ns

CNV Pulse Width (CS

t

CNVH

Mode)

10

ns

SCK Period (CS

t

SCK

Mode)

ns

VIO Above 4.5 V

10.5

ns

VIO Above 3 V

12

ns

VIO Above 2.7 V

13

ns

VIO Above 2.3 V

15

ns

SCK Period (Chain Mode)

t

SCK

ns

VIO Above 4.5 V

11.5

ns

VIO Above 3 V

13

ns

VIO Above 2.7 V

14

ns

VIO Above 2.3 V

16

ns

SCK Low Time

t

SCKL

4.5

ns

SCK High Time

t

SCKH

4.5

ns

SCK Falling Edge to Data Remains Valid

t

HSDO

3

ns

SCK Falling Edge to Data Valid Delay

t

DSDO

VIO Above 4.5 V

9.5

ns

VIO Above 3 V

11

ns

VIO Above 2.7 V

12

ns

VIO Above 2.3 V

14

ns

CNV or SDI Low to SDO D15 MSB Valid (CS

t

EN

Mode)

VIO Above 3 V

10

ns

VIO Above 2.3 V

15

ns

CNV or SDI High or Last SCK Falling Edge to SDO High Impedance (CS

t

DIS

Mode)

20

ns

SDI Valid Setup Time from CNV Rising Edge

t

SSDICNV

5

ns

SDI Valid Hold Time from CNV Rising Edge (CS

t

HSDICNV

Mode)

2

ns

SDI Valid Hold Time from CNV Rising Edge (Chain Mode)

t

HSDICNV

0

ns

SCK Valid Setup Time from CNV Rising Edge (Chain Mode)

t

SSCKCNV

5

ns

SCK Valid Hold Time from CNV Rising Edge (Chain Mode)

t

HSCKCNV

5

ns

SDI Valid Setup Time from SCK Falling Edge (Chain Mode)

t

SSDISCK

2

ns

SDI Valid Hold Time from SCK Falling Edge (Chain Mode)

t

HSDISCK

3

ns

SDI High to SDO High (Chain Mode with Busy Indicator)

t

DSDOSDI

15

ns

500µA

500µA

1.4V

TO SDO

20pF

Figure 2. Load Circuit for Digital Interface Timing

≤ 3.0V, X = 90 AND Y = 10; FOR VIO > 3.0V X = 70, AND Y = 30.

SPECIFICATIONS IN TABLE 3.

Figure 3. Voltage Levels for Timing