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TSU101ILT bảng dữ liệu(PDF) 20 Page - STMicroelectronics |
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TSU101ILT bảng dữ liệu(HTML) 20 Page - STMicroelectronics |
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20 / 33 page ![]() Application information TSU101, TSU102, TSU104 20/33 DocID024317 Rev 2 4.6 PCB layout considerations For correct operation, it is advised to add 10 nF decoupling capacitors as close as possible to the power supply pins. Minimizing the leakage from sensitive high impedance nodes on the inputs of the TSU10x series can be performed with a guarding technique. The technique consists of surrounding high impedance tracks by a low impedance track (the ring). The ring is at the same electrical potential as the high impedance node. Therefore, even if some parasitic impedance exists between the tracks, no leakage current can flow through them as they are at the same potential (see Figure 38). Figure 38. Guarding on the PCB |
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