Data Sheet

AD5121/AD5141

Rev. 0 | Page 13 of 32

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

PIN 1

INDICATOR

1

GND

2

A

3

W

4

B

11

SCLK/SCL

NOTES

1. INTERNALLY CONNECT THE

12 SDI/SDA

10

9

AD5121/

AD5141

TOP VIEW

(Not to Scale)

Figure 7. Pin Configuration

Table 9. Pin Function Descriptions

Pin No.

Mnemonic

Description

1

GND

Ground Pin, Logic Ground Reference.

2

A

Terminal A of RDAC. V

3

W

Wiper terminal of RDAC. V

4

B

Terminal B of RDAC. V

5

V

SS

Negative Power Supply. Decouple this pin with 0.1 µF ceramic capacitors and 10 µF capacitors.

6

SYNC/ADDR0

Programmable Address (ADDR0) for Multiple Package Decoding, DIS = 1.

Synchronization Data Input, Active Low. When SYNC returns high, data is loaded into the RDAC register, DIS = 0.

7

RESET

Hardware Reset Pin. Refresh the RDAC registers from EEPROM. RESET is activated at logic low. If this pin is not

8

DIS

floating.

9

V

DD

Positive Power Supply. Decouple this pin with 0.1µF ceramic capacitors and 10 µF capacitors.

10

V

LOGIC

Logic Power Supply; 1.8 V to VDD. Decouple this pin with 0.1 µF ceramic capacitors and 10 µF capacitors.

11

SCLK/SCL

SPI Serial Clock Line (SCLK). Data is clocked in at logic low transition.

12

SDI/SDA

Serial Data Input/Output (SDA), When DIS = 1.

Serial Data Input (SDI), When DIS = 0.

13

WP

Optional Write Protect. This pin prevents any changes to the present RDAC and EEPROM contents, except when

reloading the content of the EEPROM into the RDAC register. WP is activated at logic low. If this pin is not used,

14

SDO/ADDR1

Programmable Address (ADDR1) for Multiple Package Decoding, When DIS = 1.

Serial Data Output (SDO). This is an open-drain output pin, and it needs an external pull-up resistor when DIS = 0.

15

INDEP

Linear Gain Setting Mode at Power-Up. Each string resistor is loaded from its associate memory location. If

INDEP is enabled, it cannot be disabled by the software.

16

LRDAC

Load RDAC. Transfers the contents of the input register to the RDAC register. This allows asynchronous RDAC

EPAD

Internally Connect the Exposed Pad to V