FST16232 datasheet(4/6 Pages) FAIRCHILD

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AC Electrical Characteristics

Note 6: This parameter is guaranteed by design but is not tested. The bus switch contributes no propagation delay other than the RC delay of the typical On

resistance of the switch and the 50pF load capacitance, when driven by an ideal voltage source (zero output impedance).

Capacitance (Note 7)

Note 7: TA = +25°C, f = 1 MHz, Capacitance is characterized but not tested.

AC Loading and Waveforms

Note: Input driven by 50

Ω source terminated in 50 Ω

Note: CL includes load and stray capacitance

Note: Input PRR

= 1.0 MHz, t

W = 500 ns

FIGURE 1. AC Test Circuit

FIGURE 2. AC Waveforms

Symbol

Parameter

TA = −40 °C to +85 °C,

Units

Conditions

Figure

No.

CL = 50pF, RU = RD = 500Ω

VCC = 4.5 – 5.5V

VCC = 4.0V

Min

Max

Min

Max

fMAX

Maximum Clock Frequency

150

MHz

VI = OPEN

Figure 1

Figure 2

tPHL, tPLH

Prop Delay Bus to Bus (Note 6)

0.25

VI = OPEN

Figure 1

Figure 2

tPHL, tPLH

Prop Delay CLK to B or A

2.0

6.3

6.0

VI = OPEN

Figure 1

Figure 2

tPZH, tPZL

Output Enable Time

1.7

8.5

9.0

VI = 7V for tPZL,

Figure 1

Figure 2

CLK to A

= B

1 = B2

VI = OPEN for tPZH

Output Enable Time

2.0

6.5

VI = 7V for tPZL,

Figure 1

Figure 2

CLK to A or B1 or B2

VI = OPEN for tPZH

tPHZ, tPLZ

Output Disable Time

1.0

8.5

9.0

VI = 7V for tPLZ,

Figure 1

Figure 2

CLK to A or B

VI = OPEN for tPHZ

Setup Time S1, S0 before CLK ↑

2.5

2.8

Figure 1

Figure 2

Setup Time CLKEN before CLK

↑

1.8

2.0

Hold Time S1, S0 after CLK ↑

1.0

Figure 1

Figure 2

Hold Time CLKEN after CLK

↑

1.5

Pulse Width

3.1

Clock HIGH or LOW

Figure 1

Figure 2

Symbol

Parameter

Typ

Max

Units

Conditions

CIN

Control pin Input Capacitance

VCC = 5.0V

CI/O

Input/Output Capacitance

VCC = 5.0V, S0, S1 = 0V

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