MPC9449 REVISION 6 DECEMBER 21, 2012

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©2012 Integrated Device Technology, Inc.

MPC9449 Data Sheet

3.3V/2.5V 1:15 PECL/LVCMOS CLOCK FANOUT BUFFER

Figure 12. Output Transition Time Test Reference

Figure 13. Cycle-to-Cycle Jitter

Figure 14

The pin-to-pin skew is defined as the worst case difference in propagation delay be-

tween any similar delay path within a single device

GND

GND

GND

CCLK

GND

GND

PCLK

PCLK

GND

CCLK

GND

2.4

1.8 V

0.55

0.6 V

The variation in cycle time of a signal between adjacent cycles, over a ran-

dom sample of adjacent cycle pairs