ICS810001DK-21 REVISION B APRIL 13, 2010

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©2010 Integrated Device Technology, Inc.

ICS810001-21 Data Sheet

FEMTOCLOCK™ DUAL VCXO VIDEO PLL

Table 3D. CLK_SEL Function Table

Table 3E. MR Master Reset Function Table

Table 3F. FemtoCLock PLL Feedback Divider Function Table

Table 3G. PLL Output Divider Function Table

Table 3H. PLL BYPASS Logic Function Table

Input

Operation

CLK_SEL

0 (default)

Selects CLK0 as PLL reference input.

1

Selects CLK1 as PLL reference input.

Input

Operation

MR

0 (default)

Normal operation, internal dividers and the output Q are enabled.

1

Internal dividers are reset. Q output is in logic low state (with OE = 1).

Input

Operation

MF

0 (default)

Selects MF = 22. The 2nd stage PLL (FemtoClock. multiplies the output frequency of the VCXO-PLL by 22.

1

Selects MF = 24. The 2nd stage PLL (FemtoClock. multiplies the output frequency of the VCXO-PLL by 24.

Input

Operation

N1

N0

0 (default)

0 (default)

Output divider N = 4.

0

1

Output divider N = 8.

1

0

Output divider N = 12.

1

1

Output divider N = 18.

Input

Operation

nBP1

nBP0

00

VCXO-PLL mode: The input reference frequency is divided by the pre-divider P and is multiplied by the

01

Test mode: The input reference frequency is divided by the pre-divider P and the output divider N and

10

1 (default)

1 (default)

Dual PLL Mode: both PLLs are cascaded for jitter attenuation and frequency multiplication.