LDO

TCXO CLK

TCXO REQ

TCXO CLK

TCXO REQ

GPS

WLAN

TCXO

1 µF

2.2 µF

Li

CLK_REQ_1

CLK_OUT_1

CLK_REQ_2

CLK_OUT_2

GND

CDC3RL02

MCLK

_IN

MCLK _IN

C

MCLK

CDC3RL02

www.ti.com

SCHS371 – NOVEMBER 2009

APPLICATION INFORMATION

Typical Application

The CDC3RL02 is ideal for use in mobile applications as shown in Figure 1. In this example, a single low noise

TCXO system clock source is buffered to drive a mobile GPS receiver and WLAN transceiver. Each peripheral

independently requests an active clock by asserting a single clock request line (CLK_REQ_1 or CLK_REQ_2).

When both clock request lines are inactive, the CDC3RL02 enters a low current shutdown mode. In this mode,

the LDO output, CLK_OUT_1, and CLK_OUT_2 are pulled to GND and the TCXO will be unpowered.

Figure 1. Mobile Application

When either peripheral requests the clock, the CDC3RL02 will enable the LDO and power the TCXO. The TCXO

output (square wave, sine wave, or clipped sine wave) is converted to a square wave and buffered to the

requested output.

Input Clock Squarer

Figure 2 shows the input stage of the CDC3RL02. The input signal at MCLK_IN can be a square wave or sine

wave. CMCLK is an internal AC coupling capacitor that allows a direct connection from the TCXO to the

CDC3RL02 without an external capacitor.

Figure 2. Input Stage

Any external component added in the series path of the clock signal will potentially add phase noise and jitter.

The error source associated with the internal decoupling capacitor is included in the specification of the

CDC3RL02. The recommended clock frequency band of the CDC3RL02 is 10 MHz to 52 MHz for specified

functionality. All performance metrics are specified at 26 MHz. The lowest acceptable sinusoidal signal amplitude

and jitter performance.

Copyright © 2009, Texas Instruments Incorporated

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Product Folder Link(s): CDC3RL02