82576EB datasheet(3/34 Pages) INTEL

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Intel® 82576EB GbE Controller - Revisions

Revision: 2.85

Intel® 82576EB GbE Controller

September 2012

Specification Update

Revisions

Date

Revision

Description

January 2008

1.0

Initial release.

January 2008

1.1

Internal work copy.

March 2008

1.2

Updated to to show additional errata and errata addressed by A1.

March 2008

1.3

Internal work copy.

May 2008

1.9

Updated for Production stepping. Removed information that does not apply to the

production stepping removed errata fixed by documentation, mature silicon.

July 2008

2.0

Resolved documentation issues were removed. Intel Confidential stamp removed;

prepared for release on Developer.

February 2009

2.2

Non-security product information provided:

•

1.20 Product Code and Device Identification .

May 15, 2009

2.3

Spec clarification added:

•

3. PCIe: Completion Timeout Mechanism Compliance

August 6, 2009

2.4

Spec clarification added:

•

3. PCIe: Completion Timeout Mechanism Compliance

Errata updated or added:

•

6. Critical Session (Keep PHY Link Up) Mode Does Not Block All PHY Resets

Caused by PCIe Resets

•

18. JTAG: Instruction Register Functionality Doesn't Meet IEEE Std 1149-1-

2001

•

20. PCIe Elastic Buffer Noise Immunity Is Not Optimized

•

21. PCIe: Missing Replay Due to Recovery During TLP Transmission

•

22. PCIe: LTSSM Moves from L0 to Recovery Only When Receiving TS1/TS2 on

All Lanes

•

24. PCIe: Missing Completion on D3 to D0 Transition

•

25. PCIe: Completion Timeout Settings Not Loaded from EEPROM to GCR

•

26. MSI-X: Descriptor Write-back Not Triggered by EITR Expiration in MSI-X

Mode

March 5, 2010

2.5

Errata updated or added.

•

19. LED Stays On When SerDes Is Powered Down

•

27. Tx Packet Lost After PHY Speed Change Using Auto-Negotiation

•

28. PCIe: Wrong Byte Enable Bit Used for Completion Timeout Disable Bit in

Device Control 2 Register

•

29. PCIe: Completion with UR/CA Status Causes Unexpected Completion and

Completion Timeout Errors to be Reported

•

30. PCIe Hot Reset Can Lead to a Firmware Hang

•

31. MACSec: Replay Protect Not Working In Check Mode

•

32. MACSec: Packets With E=0, C=1 Should Not Be Handled as a

Authenticated MACSec Packet

•

33. MACSec: Packets With PN = 0 In The SECTAG Are Not Dropped

•

34. MACSec: SA Creation Doesn’t Clear Frame Verification Statistics

•

35. MACSec: LSECRXNUSA and LSECRXUNSA Statistic Counters Not Provided

•

36. MACSec: When MC Is MACSec owner, MAC Reset Still Clears Keys

March 8, 2010

2.6

•

36. MACSec: When MC Is MACSec owner, MAC Reset Still Clears Keys -

Additional information added; editorial changes made for clarity.

March 26, 2010

2.7

Specification clarification added:

•

4. PCIe: Receiver Dtection Circuit Design and Established Link Width

June 11, 2010

2.71

LinkSec references changed to MACSec.

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