EP610

Specification Number EP610-CI (AT) REV -

Page 3 of 9

Table 1 summarizes EP610 device features

Table 1. EP610 Device Features

Feature

EP610

EP610T

EP610-XX/B

EP610I

15 ns

15 ns

35 ns

10 ns

Counter frequency

83 MHz

83 MHz

28.5 MHz

100 MHz

Pipeline data rates

83 MHz

83 MHz

37 MHz

100 MHz

Packages

24-pin SOIC

24-pin CerDIP

24-pin PDIP

24-pin PLCC

24-pin SOIC

24-pin PDIP

28-pin PLCC

24-pin CerDIP

24-pin CerDIP

24-pin PDIP

28-pin PLCC

General

Description

Figure 2. EP610 Block Diagram

Numbers without parentheses are for DIP and SOIC packages. Numbers in parentheses are for J-lead packages.

EP610 devices have 16 macrocells, 4 dedicated input pins, 16

I/O pins, and 2 global Clock pins (see Figure 2). Each macrocell

can access signals from the global bus, which consists of the

true and complement forms of the dedicated inputs and the

true complement forms of either the output of the macrocell of

the I/O input. CLK1 is a dedicated Clock input for the registers

in macrocells 9 through 16. CLK2 is a dedicated Clock input for

registers in macrocells 1 through 8.

2 (3) INPUT

1 (2)

CLK1

3 (4)

4 (5)

5 (6)

6 (7)

7 (8)

8 (9)

9 (10)

10 (12)

11 (13) INPUT

INPUT 23 (27)

CLK2

13 (16)

22 (26)

21 (25)

20 (24)

19 (23)

18 (22)

17 (21)

16 (20)

15 (18)

INPUT 14 (17)

Global

Bus

Macrocell 9

Macrocell 10

Macrocell 11

Macrocell 12

Macrocell 13

Macrocell 14

Macrocell 15

Macrocell 16

Macrocell 9

Macrocell 10

Macrocell 11

Macrocell 12

Macrocell 13

Macrocell 14

Macrocell 15

Macrocell 16