TIMING SOLUTIONS

3

MOTOROLA

PIN CONFIGURATION

Pin

I/O

Type

Description

PCLK, PCLK

Input

PECL

Differential reference clock frequency input

CCLK

Input

LVCMOS

Reference clock input

FB_IN

Input

LVCMOS

PLL feedback clock input

QAn

Output

LVCMOS

Bank A outputs

QBn

Output

LVCMOS

Bank B outputs

QCn

Output

LVCMOS

Bank C outputs

QFB

Output

LVCMOS

Differential feedback output

REF_SEL

Input

LVCMOS

Reference clock input select

FSELA

Input

LVCMOS

Selection of bank A output frequency

FSELB

Input

LVCMOS

Selection of bank B output frequency

FSELC

Input

LVCMOS

Selection of bank C output frequency

FSEL_FB

Input

LVCMOS

Selection of feedback frequency

OE

Input

LVCMOS

Output enable

VCCA

Power supply

Analog power supply and PLL bypass. An external VCC filter is recommended for VCCA

VCC

Power supply

Core power supply

GND

Ground

Ground

GND

QA3

QA2

VCC

QA1

QA0

GND

VCC

QC3

QC4

GND

QC5

QC6

41

42

43

44

45

46

47

48

19

18

17

16

15

14

13

12

345678

36

35

34

33

32

31

30

29

20

MPC9600

Figure 2. 48 Lead Package Pinout (Top View)

FB_IN

OE

VCC

910

11

12

GND

QC0

QC1

QC2

23

22

21

24

28

27

26

25

VCC

QA6

QA5

37

38

39

40

QA4

Freescale Semiconductor, Inc.

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Go to: www.freescale.com