MPC8536DS datasheet(34/126 Pages) FREESCALE

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MPC8536E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5

Electrical Characteristics

Freescale Semiconductor

This figure shows the DDR2 and DDR3 SDRAM interface input timing diagram.

Figure 8. DDR SDRAM Input Timing Diagram

Table 17. DDR3 SDRAM Input AC Timing Specifications for 1.5-V Interface

At recommended operating conditions with GVDD of 1.5 V ± 5%. DDR3 data rate is between 606MHz and 667MHz.

Parameter

Symbol

Min

Max

Unit

Notes

AC input low voltage

VIL

—MVREF – 0.175

—

AC input high voltage

VIH

MVREF + 0.175

—

Table 18. DDR2 and DDR3 SDRAM Interface Input AC Timing Specifications

At recommended operating conditions with GVDD of 1.8 V ± 5% for DDR2 or 1.5 V ± 5% for DDR3.

Parameter

Symbol

Min

Max

Unit

Notes

Controller Skew for MDQS—MDQ/MECC

tCISKEW

—

1, 2

667 MHz

—

–240

240

—

533 MHz

—

–300

300

—

400 MHz

—

–365

365

—

Note:

1. tCISKEW represents the total amount of skew consumed by the controller between MDQS[n] and any corresponding bit that will

be captured with MDQS[n]. This should be subtracted from the total timing budget.

2. The amount of skew that can be tolerated from MDQS to a corresponding MDQ signal is called tDISKEW.This can be determined

by the following equation: tDISKEW =+/-(T/4 - abs(tCISKEW)) where T is the clock period and abs(tCISKEW) is the absolute value

of tCISKEW.

3. Maximum DDR2 and DDR3 frequency is 667MHz.

MCK[n]

tMCK

MDQ[x]

MDQS[n]

tDISKEW

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