LP2951CSD datasheet(15/43 Pages) TI1

15 / 43 page

LP2950-N, LP2951-N

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SNVS764N – JANUARY 2000 – REVISED MAY 2013

*When VIN ≤ 1.3V, the error flag pin becomes a high impedance, and the error flag voltage rises to its pull-up voltage.

Using VOUT as the pull-up voltage (see Figure 47), rather than an external 5V source, will keep the error flag voltage

under 1.2V (typ.) in this condition. The user may wish to divide down the error flag voltage using equal-value resistors

(10 k

Ω suggested), to ensure a low-level logic signal during any fault condition, while still allowing a valid high logic

level during normal operation.

Figure 46. ERROR Output Timing

Programming the Output Voltage (LP2951-N)

The LP2951-N may be pin-strapped for the nominal fixed output voltage using its internal voltage divider by tying

the output and sense pins together, and also tying the feedback and VTAP pins together. Alternatively, it may be

programmed for any output voltage between its 1.235V reference and its 30V maximum rating. As seen in

Figure 47, an external pair of resistors is required.

The complete equation for the output voltage is

where

•

VREF is the nominal 1.235V reference voltage and IFB is the feedback pin bias current, nominally -20nA

(7)

The minimum recommended load current of 1

μA forces an upper limit of 1.2 MΩ on the value of R2, if the

regulator must work with no load (a condition often found in CMOS in standby). IFB will produce a 2% typical

error in VOUT which may be eliminated at room temperature by trimming R1. For better accuracy, choosing R2 =

100 k

Ω reduces this error to 0.17% while increasing the resistor program current to 12 μA. Since the LP2951-N

typically draws 60

μA at no load with Pin 2 open-circuited, this is a small price to pay.

*See Application Hints

**Drive with TTL-high to shut down. Ground or leave open if shutdown feature is not to be used.

Note: Pins 2 and 6 are left open.

Figure 47. Adjustable Regulator

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