© 2013 Littelfuse, Inc.

Specifications are subject to change without notice.

Revised: 04/24/13

General Purpose ESD Protection - SP724 Series

Description

Features

• An Array of 4 SCR/Diode Pairs in 6-Lead SOT-23

• ESD Capability per HBM Standards

- IEC 61000-4-2, Direct Discharge .......... 8kV (Level 4)

- IEC 61000-4-2, Air Discharge...............15kV (Level 4)

- MIL STD 3015.7................................................ >8kV

• Input Protection for Applications with Power Supplies Up

to +20V (Single-Ended Voltage), and ±10V (Differential

Voltage)

• Peak Current Capability

- IEC 61000-4-5 (8/20µs) ....................................... ±3A

- Single Pulse, 100µs Pulse Width ..................... ±2.2A

• Low Input Leakage.......................................... 1nA Typical

• Low Input Capacitance.....................................3pF Typical

• Operating Temperature Range....................-40ºC to 105ºC

Applications

The SP724 is a quad array of transient voltage clamping

circuits designed to suppress ESD and other transient over-

voltage events. The SP724 is used to help protect sensitive

digital or analog input circuits on data, signal, or control

lines operating on power supplies up to 20VDC.

The SP724 is comprised of bipolar SCR/diode structures

to protect up to four independent lines by clamping

transients of either polarity to the power supply rails. The

SP724 offers very low leakage (1nA Typical) and low input

capacitance (3pF Typical). Additionally, the SP724 is rated

to withstand the IEC 61000-4-2 ESD specification for both

contact and air discharge methods to level 4.

The SP724 is connected to the sensitive input line and its

associated power supply lines. Clamping action occurs

during the transient pulse, turning on the diode and fast

triggering SCR structures when the voltage on the input

line exceeds one V

V

operation is unaffected by poor power supply regulation or

voltage fluctuations within its operating range.

• Microprocessor/Logic

Input Protection

• Data Bus Protection

• Analog Device Input

Protection

• Voltage Clamp

Pinout

Functional Block Diagram

NOTES:

1. The design of the SP724 SCR/Diode ESD Protection Arrays are

covered by Littelfuse patent 4567500.

2. The full ESD capability of the SP724 is achieved whenwiredin a

circuit that includes connection to both the V+ and V- pins. When

handling individual devices, follow proper procedures for

electrostatic discharge.

2

V+

V-

IN

3, 4 AND 6

IN

1

5

I/O

I/O

V+

I/O

I/O

V–

65

4

12

3

SP724

(SOT-23)

TOP VIEW

Notes:

1. The design of the SP724 SCR/Diode ESD Protection Arrays are covered by Littelfuse

patent 4567500.

2. The full ESD capability of the SP724 is achieved when wired in a circuit that includes

connection to both the V+ and V- pins. When handling individual devices, follow proper

procedures for electrostatic discharge.

Life Support Note:

Not Intended for Use in Life Support or Life Saving Applications

The products shown herein are not designed for use in life sustaining or life saving

applications unless otherwise expressly indicated.

SP724 Series 3pF 8kV Diode Array

Additional Information

Datasheet

Samples

Resources