M68ICS08GR datasheet(144/408 Pages) FREESCALE

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Central Processing Unit (CPU)

Technical Data

MC68HC908GR8 — Rev 4.0

144

Central Processing Unit (CPU)

MOTOROLA

The CPU sets the half-carry flag when a carry occurs between

accumulator bits 3 and 4 during an ADD or ADC operation. The half-

carry flag is required for binary-coded decimal (BCD) arithmetic

operations. The DAA instruction uses the states of the H and C flags

to determine the appropriate correction factor.

1 = Carry between bits 3 and 4

0 = No carry between bits 3 and 4

I — Interrupt mask

When the interrupt mask is set, all maskable CPU interrupts are

disabled. CPU interrupts are enabled when the interrupt mask is

cleared. When a CPU interrupt occurs, the interrupt mask is set

automatically after the CPU registers are saved on the stack, but

before the interrupt vector is fetched.

1 = Interrupts disabled

0 = Interrupts enabled

NOTE:

To maintain M6805 compatibility, the upper byte of the index register (H)

is not stacked automatically. If the interrupt service routine modifies H,

then the user must stack and unstack H using the PSHH and PULH

instructions.

After the I bit is cleared, the highest-priority interrupt request is

serviced first.

A return from interrupt (RTI) instruction pulls the CPU registers from the

stack and restores the interrupt mask from the stack. After any reset, the

interrupt mask is set and can only be cleared by the clear interrupt mask

software instruction (CLI).

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