M68ICS08GR datasheet(135/408 Pages) FREESCALE

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Computer Operating Properly (COP)

I/O Signals

MC68HC908GR8 — Rev 4.0

Technical Data

MOTOROLA

Computer Operating Properly (COP)

135

In monitor mode, the COP is disabled if the RST pin or the IRQ1 is held

at VTST. During the break state, VTST on the RST pin disables the COP.

NOTE:

Place COP clearing instructions in the main program and not in an

interrupt subroutine. Such an interrupt subroutine could keep the COP

from generating a reset even while the main program is not working

properly.

9.4 I/O Signals

The following paragraphs describe the signals shown in Figure 9-1.

9.4.1 CGMXCLK

CGMXCLK is the crystal oscillator output signal. CGMXCLK frequency

is equal to the crystal frequency.

9.4.2 STOP Instruction

The STOP instruction clears the COP prescaler.

9.4.3 COPCTL Write

Writing any value to the COP control register (COPCTL) (see COP

Control Register) clears the COP counter and clears bits 12 through 5 of

the prescaler. Reading the COP control register returns the low byte of

the reset vector.

9.4.4 Power-On Reset

The power-on reset (POR) circuit clears the COP prescaler 4096

CGMXCLK cycles after power-up.

9.4.5 Internal Reset

An internal reset clears the COP prescaler and the COP counter.

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