M68ICS08GR datasheet(103/408 Pages) FREESCALE

103 / 408 page

Clock Generator Module (CGMC)

Functional Description

MC68HC908GR8 — Rev 4.0

Technical Data

MOTOROLA

Clock Generator Module (CGMC)

103

The operating range of the VCO is programmable for a wide range of

frequencies and for maximum immunity to external noise, including

supply and CGM/XFC noise. The VCO frequency is bound to a range

from roughly one-half to twice the center-of-range frequency, fVRS.

Modulating the voltage on the CGM/XFC pin changes the frequency

within this range. By design, fVRS is equal to the nominal center-of-range

frequency, fNOM, (38.4 kHz) times a linear factor, L, and a power-of-two

factor, E, or (L

× 2E)f

NOM.

CGMRCLK is the PLL reference clock, a buffered version of CGMXCLK.

CGMRCLK runs at a frequency, fRCLK, and is fed to the PLL through a

programmable modulo reference divider, which divides fRCLK by a

factor, R. The divider’s output is the final reference clock, CGMRDV,

running at a frequency, fRDV =fRCLK/R. With an external crystal

(30 kHz–100 kHz), always set R = 1 for specified performance. With an

external high-frequency clock source, use R to divide the external

frequency to between 30 kHz and 100 kHz.

The VCO’s output clock, CGMVCLK, running at a frequency, fVCLK, is

fed back through a programmable prescale divider and a programmable

modulo divider. The prescaler divides the VCO clock by a power-of-two

factor P and the modulo divider reduces the VCO clock by a factor, N.

The dividers’ output is the VCO feedback clock, CGMVDV, running at a

frequency, fVDV =fVCLK/(N × 2

P). (See Programming the PLL for more

information.)

The phase detector then compares the VCO feedback clock, CGMVDV,

with the final reference clock, CGMRDV. A correction pulse is generated

based on the phase difference between the two signals. The loop filter

then slightly alters the DC voltage on the external capacitor connected

to CGM/XFC based on the width and direction of the correction pulse.

The filter can make fast or slow corrections depending on its mode,

described in Acquisition and Tracking Modes. The value of the external

capacitor and the reference frequency determine the speed of the

corrections and the stability of the PLL.

The lock detector compares the frequencies of the VCO feedback clock,

CGMVDV, and the final reference clock, CGMRDV. Therefore, the

speed of the lock detector is directly proportional to the final reference

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

M68ICS08GR bảng dữ liệu(PDF) 103 Page - Freescale Semiconductor, Inc

M68ICS08GR bảng dữ liệu(HTML) 103 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL