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M68ICS08GR bảng dữ liệu(PDF) 367 Page - Freescale Semiconductor, Inc |
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M68ICS08GR bảng dữ liệu(HTML) 367 Page - Freescale Semiconductor, Inc |
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367 / 408 page ![]() Electrical Specifications 3.0 V DC Electrical Characteristics MC68HC908GR8 — Rev 4.0 Technical Data MOTOROLA Electrical Specifications 367 Pullup resistors (as input only) Ports PTA3/KBD37–PTA0/KBD0, PTC1–PTC0, PTD6/T2CH0–PTD0/SS RPU 20 45 65 k Ω Capacitance Ports (as input or output) COut CIn — — — — 12 8 pF Monitor mode entry voltage VTST VDD +2.5 — 8V Low-voltage inhibit, trip falling voltage – target VTRIPF 2.35 2.60 2.70 V Low-voltage inhibit, trip rising voltage – target VTRIPR 2.45 2.66 2.80 V Low-voltage inhibit reset/recover hysteresis – target (VTRIPF + VHYS = VTRIPR) VHYS — 60 — mV POR rearm voltage(8) VPOR 0 — 100 mV POR reset voltage(9) VPORRST 0 700 800 mV POR rise time ramp rate(10) RPOR 0.02 —— V/ms Notes: 1. VDD = 3.0 Vdc ± 10%, VSS = 0 Vdc, TA = TL to TH, unless otherwise noted 2. Typical values reflect average measurements at midpoint of voltage range, 25 °C only. 3. Run (operating) IDD measured using external square wave clock source (fosc = 16.4 MHz). All inputs 0.2 V from rail. No dc loads. Less than 100 pF on all outputs. CL = 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly affects run IDD. Measured with all modules enabled. 4. Wait IDD measured using external square wave clock source (fosc = 16.4 MHz). All inputs 0.2 V from rail. No dc loads. Less than 100 pF on all outputs. CL = 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly affects wait IDD. Measured with PLL and LVI enabled. 5. Stop IDD is measured with OSC1 = VSS. 6. Stop IDD with TBM enabled is measured using an external square wave clock source (fOSC = 32.8 KHz). All inputs 0.2 V from rail. No dc loads. Less than 100 pF on all outputs. All inputs configured as inputs. 7. Pullups and pulldowns are disabled. 8. Maximum is highest voltage that POR is guaranteed. 9. Maximum is highest voltage that POR is possible. 10. If minimum VDD is not reached before the internal POR reset is released, RST must be driven low externally until minimum VDD is reached. Table 23-5. 3.0 V DC Electrical Characteristics Characteristic(1) Symbol Min Typ(2) Max Unit Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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