M68ICS08GR datasheet(331/408 Pages) FREESCALE

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Timebase Module (TBM)

Timebase Register Description

MC68HC908GR8 — Rev 4.0

Technical Data

MOTOROLA

Timebase Module (TBM)

331

21.5 Timebase Register Description

The timebase has one register, the TBCR, which is used to enable the

timebase interrupts and set the rate.

TBIF — Timebase Interrupt Flag

This read-only flag bit is set when the timebase counter has rolled

over.

1 = Timebase interrupt pending

0 = Timebase interrupt not pending

TBR2:TBR0 — Timebase Rate Selection

These read/write bits are used to select the rate of timebase interrupts

as shown in Table 21-1.

Address:

$001C

Bit 7

654321

Bit 0

Read:

TBIF

TBR2

TBR1

TBR0

TBIE

TBON

Reserved

Write:

TACK

Reset:

00000000

= Unimplemented

Figure 21-2. Timebase Control Register (TBCR)

Table 21-1. Timebase Rate Selection for OSC1 = 32.768 kHz

TBR2

TBR1

TBR0

Divider

Timebase Interrupt Rate

32,768

1000

8192

250

2048

62.5

128

256

~ 3.9

512

1024

2048

~0.5

4096

~0.24

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