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Serial Peripheral Interface (SPI)

Technical Data

MC68HC908GR8 — Rev 4.0

302

Serial Peripheral Interface (SPI)

MOTOROLA

The SPR1 and SPR0 bits control the baud rate generator and determine

the speed of the shift register. See SPI Status and Control Register.

Through the SPSCK pin, the baud rate generator of the master also

controls the shift register of the slave peripheral.

As the byte shifts out on the MOSI pin of the master, another byte shifts

in from the slave on the master’s MISO pin. The transmission ends when

the receiver full bit, SPRF, becomes set. At the same time that SPRF

becomes set, the byte from the slave transfers to the receive data

Software clears SPRF by reading the SPI status and control register with

SPRF set and then reading the SPI data register. Writing to the SPI data

20.5.2 Slave Mode

The SPI operates in slave mode when the SPMSTR bit is clear. In slave

mode, the SPSCK pin is the input for the serial clock from the master

MCU. Before a data transmission occurs, the SS pin of the slave SPI

must be at logic 0. SS must remain low until the transmission is

complete. See Mode Fault Error.

In a slave SPI module, data enters the shift register under the control of

the serial clock from the master SPI module. After a byte enters the shift

SPRF bit is set. To prevent an overflow condition, slave software then

must read the receive data register before another full byte enters the

shift register.

The maximum frequency of the SPSCK for an SPI configured as a slave

is the bus clock speed (which is twice as fast as the fastest master

SPSCK clock that can be generated). The frequency of the SPSCK for

an SPI configured as a slave does not have to correspond to any SPI

baud rate. The baud rate only controls the speed of the SPSCK

generated by an SPI configured as a master. Therefore, the frequency

of the SPSCK for an SPI configured as a slave can be any frequency

less than or equal to the bus speed.

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