IP1837 datasheet(25/40 Pages) IRF

25 / 40 page

iP1837

Highly Integrated 35A Single‐input Voltage,

Synchronous Buck Regulator

March 5, 2012 | V1.26

97600

These result in:

FLC=25.58kHz

FESR=4.4MHz

Fs/2=300kHz

Select crossover frequency Fo=110 kHz

Since FLC<Fo<Fs/2<FESR, Type III is selected to place

the pole and zeros.

Detailed calculation of compensation Type III:

Desired Phase Margin Θ = 80°

kHz

9.62

sin













kHz

1257.31

sin













kHz

4.81

0.5



kHz

300

0.5



Select: C7 = 2.2nF

Calculate: R3, C3 and C4:

kΩ

4.75

;







Select: R3 = 4.22 kΩ

8.2

Select

nF,

7.84

;





120

Select

125.71

;





Calculate: R10, R8 and R9:

Ω

57.6

Select

Ω

;





kΩ

7.46

;





Select: R8 = 7.5 kΩ

PROGRAMMING THE CURRENT‐LIMIT

The Current‐Limit threshold can be set by connecting

a resistor (ROCSet) from the SW pin to the OCSet pin.

The resistor can be selected by using Table 2.

In order to set a trip current of 40A, we may select

ROCSet = 54.9K, using Table 2.

SETTING THE POWER GOOD THRESHOLD

A window comparator internally sets a lower Power Good

threshold at 0.51V and an upper Power Good threshold at

0.7V. When the voltage at the Voso pin is within the

window set by these thresholds, PGood is asserted.

The power good output PGD is an open drain output.

Hence, it is necessary to use a pull up resistor RPG from

PGD pin to Vcc. The value of the pull‐up resistor must be

chosen such as to limit the current flowing into the PGD

pin, when the output voltage is not in regulation, to less

than 5mA. A typical value used is 10kΩ.

It must be noted that if the voltage on Voso exceeds the

upper threshold 0.7V, not only is PGD de‐asserted, but also

an overvoltage fault is flagged, following which, even if the

overvoltage condition gets resolved, the converter can be

re‐started only by cycling Vcc or Enable.

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