PI7C8140AMA datasheet(32/82 Pages) PERICOM

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PI7C8140A

2-PORT PCI-TO-PCI BRIDGE

Page 32 of 82

March 20, 2007 – Revision 1.01

Use more than 16 clocks to accept this transaction.

For delayed read transactions:

The transaction is being entered into the delayed transaction queue.

The read request has already been queued, but read data is not yet available.

Data has been read from target, but it is not yet at head of the read data queue or a posted write

transaction precedes it.

The delayed transaction queue is full, and the transaction cannot be queued.

A delayed read request with the same address and bus command has already been queued.

A locked sequence is being propagated across the bridge, and the read transaction is not a locked

transaction.

The bridge is currently discarding previously pre-fetched read data.

The target bus is locked and the write transaction is a locked transaction.

Use more than 16 clocks to accept this transaction.

For posted write transactions:

The posted write data buffer does not have enough space for address and at least one DWORD of

write data.

A locked sequence is being propagated across the bridge, and the write transaction is not a locked

transaction.

When a target retry is returned to the initiator of a delayed transaction, the initiator must repeat the

transaction with the same address and bus command as well as the data if it is a write transaction,

within the time frame specified by the master timeout value. Otherwise, the transaction is discarded

from the buffers.

2.8.4.2 TARGET DISCONNECT

The bridge returns a target disconnect to an initiator when one of the following conditions is met:

Bridge hits an internal address boundary.

Bridge cannot accept any more write data.

Bridge has no more read data to deliver.

See Section 2.5.4 for a description of write address boundaries, and Section 2.6.4 for a description of

read address boundaries.

2.8.4.3 TARGET ABORT

The bridge returns a target abort to an initiator when one of the following conditions is met:

The bridge is returning a target abort from the intended target.

When the bridge returns a target abort to the initiator, it sets the signaled target abort bit in the

status register corresponding to the initiator interface.

07-0067

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