PI7C8140AMAE datasheet(49/82 Pages) PERICOM

49 / 82 page

PI7C8140A

2-PORT PCI-TO-PCI BRIDGE

Page 49 of 82

March 20, 2007 – Revision 1.01

The bridge has detected P_PERR# asserted on an upstream posted write transaction or S_PERR#

asserted on a downstream posted write transaction.

The bridge did not detect the parity error as a target of the posted write transaction.

The parity error response bit on the command register and the parity error response bit on the

bridge control register must both be set.

The SERR# enable bit must be set in the command register.

Table 5-7. Assertion of P_SERR# for Data Parity Errors

P_SERR#

Transaction Type

Direction

Bus Where Error

Was Detected

Primary / Secondary Parity

Error Response Bits

1 (de-asserted)

Read

Downstream

Primary

x / x

Read

Downstream

Secondary

x / x

Read

Upstream

Primary

x / x

Read

Upstream

Secondary

x / x

Posted Write

Downstream

Primary

x / x

2 (asserted)

Posted Write

Downstream

Secondary

1 / 1

Posted Write

Upstream

Primary

1 / 1

Posted Write

Upstream

Secondary

x / x

Delayed Write

Downstream

Primary

x / x

Delayed Write

Downstream

Secondary

x / x

Delayed Write

Upstream

Primary

x / x

Delayed Write

Upstream

Secondary

x / x

X = don’t care

The parity error was detected on the target (secondary) bus but not on the initiator (primary) bus.

The parity error was detected on the target (primary) bus but not on the initiator (secondary) bus.

5.4

SYSTEM ERROR (SERR#) REPORTING

The bridge uses the P_SERR# signal to report conditionally a number of system error conditions in

addition to the special case parity error conditions described in Section 5.2.3.

Whenever assertion of P_SERR# is discussed in this document, it is assumed that the following

conditions apply:

For the bridge to assert P_SERR# for any reason, the SERR# enable bit must be set in the

command register.

Whenever the bridge asserts P_SERR#, the bridge must also set the signaled system error bit in the

status register.

In compliance with the PCI-to-PCI Bridge Architecture Specification, the bridge asserts P_SERR#

when it detects the secondary SERR# input, S_SERR#, asserted and the SERR# forward enable bit is

set in the bridge control register. In addition, the bridge also sets the received system error bit in the

secondary status register.

The bridge also conditionally asserts P_SERR# for any of the following reasons:

Target abort detected during posted write transaction

Master abort detected during posted write transaction

Posted write data discarded after 2

24 (default) attempts to deliver (224 target retries received)

Parity error reported on target bus during posted write transaction (see previous section)

Delayed write data discarded after 2

24 (default) attempts to deliver (224 target retries received)

07-0067

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