TSB81BA3DI datasheet(29/61 Pages) TI1

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TSB81BA3D, TSB81BA3DI

IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER

SLLS559E − DECEMBER 2002 − REVISED JUNE 2006

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

PRINCIPLES OF OPERATION (1394a−2000 INTERFACE)

There are four operations that may occur on the PHY-LLC interface: link service request, status transfer, data

transmit, and data receive. The LLC issues a service request to read or write a PHY register, to request the PHY

to gain control of the serial-bus in order to transmit a packet, or to control arbitration acceleration.

The PHY may initiate a status transfer either autonomously or in response to a register read request from the

LLC.

The PHY initiates a receive operation whenever a packet is received from the serial-bus.

The PHY initiates a transmit operation after winning control of the serial-bus following a bus-request by the LLC.

The transmit operation is initiated when the PHY grants control of the interface to the LLC.

Table 10 and Table 11 show the encoding of the CTL0−CTL1 bus.

Table 10. CTL Encoding When PHY Has Control of the Bus

CTL0

CTL1

NAME

DESCRIPTION

Idle

No activity (this is the default mode)

Status

Status information is being sent from the PHY to the LLC.

Receive

An incoming packet is being sent from the PHY to the LLC.

Grant

The LLC has been given control of the bus to send an outgoing packet.

Table 11. CTL Encoding When LLC Has Control of the Bus

CTL0

CTL1

NAME

DESCRIPTION

Idle

The LLC releases the bus (transmission has been completed)

Hold

The LLC is holding the bus while data is being prepared for transmission, or indicating that another packet is to

be transmitted (concatenated) without arbitrating

Transmit

An outgoing packet is being sent from the LLC to the PHY

Reserved

None

LLC service request

To request access to the bus, to read or write a PHY register, or to control arbitration acceleration, the LLC sends

a serial bit stream on the LREQ terminal as shown in Figure 11.

Each cell represents one clock sample time, and n is the number of bits in the request stream.

LR1

LR2

LR3

LR (n-2)

LR0

LR (n-1)

Figure 11. LREQ Request Stream

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