MC908AB32CFUE datasheet(77/392 Pages) FREESCALE

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EEPROM

MC68HC908AB32 — Rev. 1.1

Technical Data

Freescale Semiconductor

EEPROM

NOTE:

A. Setting the EELAT bit configures the address and data buses to latch

data for erasing the array. Only valid EEPROM addresses will be

latched. If EELAT is set, other writes to the EECR will be allowed after a

valid EEPROM write.

B. If more than one valid EEPROM writes occur, the last address and

data will be latched, overriding the previous address and data. Once

written data to the desired address, do not read EEPROM locations

other than the written location. (Reading an EEPROM location returns

the latched data, and causes the read address to be latched.)

EENVR is not affected by block or bulk erase.

C. The EEPGM bit cannot be set if the EELAT bit is cleared or a non-

valid EEPROM address is latched. This is to ensure proper

programming sequence. Once EEPGM is set, do not read any EEPROM

locations, otherwise the current erase cycle will be unsuccessful. When

EEPGM is set, the erase mode cannot be changed, and the on-board

erasing sequence will be activated.

D. The delay time for the EEPGM bit to be cleared in AUTO mode is less

than tEBYTE / tEBLOCK / tEBULK. However, on other MCUs, this delay time

may be different. For forward compatibility, software should not make

any dependency on this delay time.

E. Any attempt to clear both EEPGM and EELAT bits with a single

instruction will only clear EEPGM. This is to allow time for removal of

high voltage from the EEPROM array.

5.10 Low Power Modes

The WAIT and STOP instructions can put the MCU in low power

consumption standby modes.

5.10.1 Wait Mode

The WAIT instruction does not affect the EEPROM. It is possible to start

the program or erase sequence on the EEPROM and put the MCU in

wait mode.

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