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MC68HC bảng dữ liệu(PDF) 97 Page - Freescale Semiconductor, Inc |
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MC68HC bảng dữ liệu(HTML) 97 Page - Freescale Semiconductor, Inc |
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97 / 124 page ![]() TIMING SYSTEM TECHNICAL DATA 9-11 polled or interrupt driven system. Each bit of TFLG1 corresponds to a bit in TMSK1 in the same position. Clear flags by writing a one to the corresponding bit position(s). OC1F–OC5F — Output Compare x Flag Set each time the counter matches output compare x value I4/O5F — Input Capture 4/Output Compare 5 Flag Set by IC4 or OC5, depending on the function enabled by I4/O5 bit in PACTL IC1F–IC3F — Input Capture x Flag Set each time a selected active edge is detected on the ICx input line 9.3.9 Timer Interrupt Mask 2 Register Use this 8-bit register to enable or inhibit timer overflow and real-time interrupts. The timer prescaler control bits are included in this register. TOI — Timer Overflow Interrupt Enable 0 = TOF interrupts disabled 1 = Interrupt requested when TOF is set to one RTII — Real-time Interrupt Enable Refer to 9.4 Real-Time Interrupt. PAOVI — Pulse Accumulator Overflow Interrupt Enable Refer to 9.6 Pulse Accumulator. PAII — Pulse Accumulator Input Edge Interrupt Enable Refer to 9.6 Pulse Accumulator. NOTE Bits in TMSK2 correspond bit for bit with flag bits in TFLG2. Ones in TMSK2 enable the corresponding interrupt sources. TFLG1 — Timer Interrupt Flag 1 $0023 Bit 7 654321 Bit 0 OC1F OC2F OC3F OC4F I4/O5F IC1F IC2F IC3F RESET: 0000000 0 TMSK2 — Timer Interrupt Mask 2 $0024 Bit 7 654321 Bit 0 TOI RTII PAOVI PAII 0 0 PR1 PR0 RESET: 0000000 0 Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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