M68000 datasheet(76/189 Pages) FREESCALE

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M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL

MOTOROLA

executing a reset instruction is ignored. Since the processor asserts the RESET signal for

124 clock cycles during execution of a reset instruction, an external reset should assert

RESET for at least 132 clock periods.

5.6 THE RELATIONSHIP OF

DTACK, BERR, AND HALT

To properly control termination of a bus cycle for a retry or a bus error condition, DTACK,

BERR, and HALT should be asserted and negated on the rising edge of the processor

clock. This relationship assures that when two signals are asserted simultaneously, the

required setup time (specification #47, Section 9 Electrical Characteristics) for both of

them is met during the same bus state. External circuitry should be designed to

incorporate this precaution. A related specification, #48, can be ignored when DTACK,

BERR, and HALT are asserted and negated on the rising edge of the processor clock.

The possible bus cycle termination can be summarized as follows (case numbers refer to

Table 5-5).

Normal Termination:

DTACK is asserted. BERR and HALT remain negated (case 1).

Halt Termination:

HALT is asserted coincident with or preceding DTACK, and

BERR remains negated (case 2).

Bus Error Termination:

BERR is asserted in lieu of, coincident with, or preceding

DTACK (case 3). In the MC68010, the late bus error also,

BERR is asserted following DTACK (case 4). HALT remains

negated and BERR is negated coincident with or after DTACK.

Retry Termination:

HALT and BERR asserted in lieu of, coincident with, or before

DTACK (case 5). In the MC68010, the late retry also, BERR

and HALT are asserted following DTACK (case 6). BERR is

negated coincident with or after DTACK. HALT must be held at

least one cycle after BERR.

Table 5-1 shows the details of the resulting bus cycle termination in the M68000

microprocessors for various combinations of signal sequences.

Freescale Semiconductor, Inc.

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