AD9735BBC datasheet(32/72 Pages) AD

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AD9734/AD9735/AD9736

Rev. A | Page 32 of 72

SYNC CONTROLLER (SYNC_CNT) REGISTERS (REG. 7, REG. 8)

ADDR

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0x07

SYNC_CNT1

FIFOSTAT3

FIFOSTAT2

FIFOSTAT1

FIFOSTAT0

VALID

SCHANGE

PHOF<1>

PHOF<0>

0x08

SYNC_CNT2

SSURV

SAUTO

SFLT<3>

SFLT<2>

SFLT<1>

SFLT<0>

RESERVED

STRH<0>

Table 14. Sync Controller Register Bit Descriptions

Bit Name

Read/Write

Description

FIFOSTAT<2:0>

READ

Position of FIFO read counter ranges from 0 to 7.

FIFOSTAT<3>

READ

0, SYNC logic OK.

1, error in SYNC logic.

VALID

READ

0, FIFOSTAT<3:0> is not valid yet.

1, FIFOSTAT<3:0> is valid after a reset.

SCHANGE

READ

0, no change in FIFOSTAT<3:0>.

1, FIFOSTAT<3:0> has changed since the previous measurement cycle when SSURV = 1 (surveillance mode

active).

PHOF<1:0>

WRITE

00, change the readout counter.

READ

Current setting of the readout counter (PHOF<1:0>) in surveillance mode (SSURV = 1) after an interrupt.

Current calculated optimal readout counter value in AUTO mode (SAUTO = 1).

SSURV

WRITE

0, the controller stops after completion of the current measurement cycle.

1, continuous measurements are taken and an interrupt is issued if the readout counter drifts beyond the

threshold value.

SAUTO

WRITE

0, readout counter (PHOF<3:0>) is not automatically updated.

1, continuously starts measurement cycles and updates the readout counter according to the

measurement.

NOTE: SSURV (Reg. 8, Bit 7) must be set to 1 and the SYNC IRQ (Reg. 1, Bit 2) must be set to 0 for AUTO

mode.

SFLT<3:0>

WRITE

0x0, average filter length, FIFOSTAT = FIFOSTAT + Delta FIFOSTAT/2 ^ SFLT<3:0>; values greater than 12

(0x0C) are clipped to 12.

STRH<0>

WRITE

0, if FIFOSTAT<2:0> = 0 or 7, a sync interrupt is generated.

1, if FIFOSTAT<2:0> = 0, 1, 6 or 7, a sync interrupt is generated.

CROSS CONTROLLER (CROS_CNT) REGISTERS (REG. 10, REG. 11)

ADDR

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0x0A

CROS_CNT1

–

UPDEL<5>

UPDEL<4>

UPDEL<3>

UPDEL<2>

UPDEL<1>

UPDEL<0>

0x0B

CROS_CNT2

–

DNDEL<5>

DNDEL<4>

DNDEL<3>

DNDEL<2>

DNDEL<1>

DNDEL<0>

Table 15. Cross Controller Register Description

Bit Name

Read/Write

Description

UPDEL<5:0>

WRITE

0x00, move the differential output stage switching point up, set to 0 if DNDEL is non-zero.

DNDEL<5:0>

WRITE

0x00, move the differential output stage switching point down, set to 0 if UPDEL is non-zero.

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