AD9944KCPRL datasheet(6/20 Pages) AD

tên linh kiện	AD9944KCPRL

Giải thích chi tiết về linh kiện	Complete 10-Bit and 12-Bit, 25 MHz CCD Signal Processors

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AD9943/AD9944

Rev. B | Page 6 of 20

TIMING SPECIFICATIONS

CL = 20 pF, fSAMP = 25 MHz. See CCD-mode timing in Figure 14 and Figure 15, and serial timing in Figure 10 and Figure 11.

Table 5.

Parameter

Symbol

Min

Typ

Max

Unit

SAMPLE CLOCKS

DATACLK, SHP, SHD Clock Period

tCONV

DATACLK High/Low Pulse Width

tADC

SHP Pulse Width

tSHP

SHD Pulse Width

tSHD

CLPOB Pulse Width1

tCOB

Pixels

SHP Rising Edge to SHD Falling Edge

tS1

SHP Rising Edge to SHD Rising Edge

tS2

Internal Clock Delay

tID

3.0

DATA OUTPUTS

Output Delay

tOD

9.5

Pipeline Delay

Cycles

SERIAL INTERFACE

Maximum SCK Frequency

fSCLK

MHz

SL to SCK Setup Time

tLS

SCK to SL Hold Time

tLH

SDATA Valid to SCK Rising Edge Setup

tDS

SCK Falling Edge to SDATA Valid Hold

tDH

1 Minimum CLPOB pulse width is for functional operation only. Wider typical pulses are recommended to achieve low noise clamp performance.

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