PIC16CE623 datasheet(29/114 Pages) MICROCHIP

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 1998-2013 Microchip Technology Inc.

DS40182D-page 29

PIC16CE62X

6.0

EEPROM PERIPHERAL

OPERATION

The PIC16CE623/624/625 each have 128 bytes of

EEPROM data memory. The EEPROM data memory

supports a bi-directional, 2-wire bus and data transmis-

sion protocol. These two-wires are serial data (SDA)

and serial clock (SCL), and are mapped to bit1 and bit2,

respectively, of the EEINTF register (SFR 90h). In addi-

tion, the power to the EEPROM can be controlled using

bit0 (EEVDD) of the EEINTF register.

For most appli-

cations, all that is required is calls to the following func-

tions:

; Byte_Write: Byte write routine

;

Inputs: EEPROM Address

EEADDR

;

EEPROM Data

EEDATA

;

Outputs:

Return 01 in W if OK, else

;

return 00 in W

;

; Read_Current: Read EEPROM at address

currently held by EE device.

;

Inputs: NONE

;

Outputs:

EEPROM Data

EEDATA

;

Return 01 in W if OK, else

;

return 00 in W

;

; Read_Random: Read EEPROM byte at supplied

; address

;

Inputs: EEPROM Address

EEADDR

;

Outputs:

EEPROM Data

EEDATA

;

Return 01 in W if OK,

;

else return 00 in W

The code for these functions is available on our web

site (www.microchip.com). The code will be accessed

by either including the source code FL62XINC.ASM or

by linking FLASH62X.ASM. FLASH62.IMC provides

external definition to the calling program.

6.0.1

SERIAL DATA

SDA is a bi-directional pin used to transfer addresses

and data into and data out of the memory.

For normal data transfer, SDA is allowed to change only

during SCL low. Changes during SCL high are

reserved for indicating the START and STOP condi-

tions.

6.0.2

SERIAL CLOCK

This SCL input is used to synchronize the data transfer

to and from the memory.

6.0.3

EEINTF REGISTER

The EEINTF register (SFR 90h) controls the access to

the EEPROM. Register 6-1 details the function of each

bit. User code must generate the clock and data sig-

nals.

U-0

R/W-1





EESCL

EESDA

EEVDD

= Readable bit

W = Writable bit

= Unimplemented bit,

read as ‘0’

- n = Value at POR reset

bit7

bit0

bit 7-3:

Unimplemented: Read as '0'

bit 2:

EESCL: Clock line to the EEPROM

= Clock high

= Clock low

bit 1:

EESDA: Data line to EEPROM

= Data line is high (pin is tri-stated, line is pulled high by a pull-up resistor)

= Data line is low

bit 0:

EEVDD: VDD control bit for EEPROM

= VDD is turned on to EEPROM

= VDD is turned off to EEPROM (all pins are tri-stated and the EEPROM is powered down)

Note:

EESDA, EESCL and EEVDD will read ‘0’ if EEVDD is turned off.

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