QG80331M800 datasheet(64/67 Pages) INTEL

64 / 67 page

Specification Update

Intel® 80331 I/O Processor

Documentation Changes

07:06

002

Reserved.

05:04

002

ODT Termination Value: Determines the termination value of the On Die Termination for both Banks

(controlled by ODT[1:0]). Applies to DDR-II SDRAM memory type only.

•

00 Disabled

•

01 75 ohm

•

10 150 ohm

•

11 reserved

Reserved

Varies with

external state

MEM_TYPE

at PCI bus

reset

DDR Type: Identifies the selected DDR generation of SDRAM based on the MEM_TYPE reset strap.

0 = DDR-II (supported speed of 400 MHz) - MEM_TYPE Deasserted.

1 = DDR (supported speed of 333 MHz) - MEM_TYPE Asserted.

Data Bus Width: Indicates the width of the data bus. See Section 8.3.3.4, “32-bit Data Bus Width” on

page 458.

0 = 64 bits

1 = 32 bits

DIMM Type: Selects unbuffered or registered DIMM operating modes for the MCU.

0 = Unbuffered*

1 = Registered

NOTE: Unbuffered DDR SDRAM memory subsystems will use the Unbuffered mode.

Table 236.

DDR SDRAM Control Register 0 - SDCR0 (Sheet 2 of 2)

Bit

Default

Description

PCI

IOP

Attributes

Attribute Legend:

RV = Reserved

PR = Preserved

RS = Read/Set

RW = Read/Write

RC = Read Clear

RO = Read Only

NA = Not Accessible

Intel XScale® core Local Bus Address

FFFF E504H

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