SC189ASK.TRT datasheet(21/24 Pages) SEMICOA

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SC189

Figure 7 — Recommended PCB Top & Bottom Layer

Layout for MLPD-UT6 2x2 Package

PCB Layout Considerations

The layout diagram in figure 7 and figure 8 shows a

recommended PCB for MLPD-UT6 2x2 and SOT23-5

package, respectively. Fundamental layout rules must

be followed since the layout is critical for achieving the

performance specified in the Electrical Characteristics

table. Poor layout can degrade the performance of the DC-

DC converter and can contribute to EMI problems, ground

bounce, and resistive voltage losses. Poor regulation and

instability can result.

The following guidelines are recommended when

developing a PCB layout:

Theinputcapacitor,C

IN should be placed as close to the

VIN and GND pins as possible. This capacitor provides

a low impedance loop for the pulsed currents present

at the buck converter’s input. Use short wide traces

to connect as closely to the IC as possible. This will

minimize EMI and input voltage ripple by localizing

the high frequency current pulses.

Keep the LX pin traces as short as possible to minimize

pickup of high frequency switching edges to other

parts of the circuit. C

OUT and L should be connected as

close as possible between the LX and GND pins, with

a direct return to the GND pin from C

OUT.

Route the output voltage feedback/sense path away

from inductor and LX node to minimize noise and

magnetic interference.

Use a ground plane referenced to the SC189 GND pin.

Use several vias to connect to the component side

ground to further reduce noise and interference on

sensitive circuit nodes.

If possible, minimize the resistance from theVOUT and

GND pins to the load.This will reduce the voltage drop

on the ground plane and improve the load regulation.

And it will also improve the overall efficiency by

reducing the copper losses on the output and ground

planes.

Applications Information (continued)

(a) Top layer for MLPD-UT6 2x2 package

(b) Bottom layer for MLPD 2x2 package

VIN

GND

VOUT

GND

Figure 8 — Recommended PCB Top & Bottom Layer

Layout for SOT23-5 Package

(a) Top layer for SOT23-5 package

(b) Bottom layer for SOT23-5 package

GND

VOUT

CIN

COUT

VIN

GND

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