LSM330DLC datasheet(16/66 Pages) STMICROELECTRONICS

tên linh kiện	LSM330DLC

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Module specifications

LSM330DLC

16/66

Doc ID 022162 Rev 2

2.4

Communication interface characteristics

2.4.1

SPI - serial peripheral interface

Subject to general operating conditions for Vdd and TOP.

Figure 3.

SPI slave timing diagram(c)(d)

Data on CS, SPC, SDI and SDO refer to pins: CS_A, CS_G, SCL_A/G, SDA_A/G, SDO_A / SDO_G.

Table 6.

SPI slave timing values

Symbol

Parameter

Value (1)

Unit

Min

Max

tc(SPC)

SPI clock cycle

100

fc(SPC)

SPI clock frequency

MHz

tsu(CS)

CS setup time

th(CS)

CS hold time

tsu(SI)

SDI input setup time

th(SI)

SDI input hold time

tv(SO)

SDO valid output time

th(SO)

SDO output hold time

tdis(SO)

SDO output disable time

Values are guaranteed at 10 MHz clock frequency for SPI with both 4 and 3 wires, based on characterization results. Not

tested in production.

The SDO output line features an internal pull-up.

Measurement points are done at 0.2·Vdd_IO and 0.8·Vdd_IO, for both input and output ports.

SPC

SDI

SDO

tsu(CS)

tv(SO)

th(SO)

th(SI)

tsu(SI)

th(CS)

tdis(SO)

tc(SPC)

MSB IN

MSB OUT

LSB OUT

LSB IN

(3)

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