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WM8952ECS/RV bảng dữ liệu(PDF) 29 Page - Wolfson Microelectronics plc |
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WM8952ECS/RV bảng dữ liệu(HTML) 29 Page - Wolfson Microelectronics plc |
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29 / 72 page ![]() Pre Production WM8952 w PP, Rev 3.1, June 2011 29 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R42 (2Ah) ALC Control 4 1 ALCZC 0 (zero cross off) ALC uses zero cross detection circuit. 0 = Disabled (recommended) 1 = Enabled Table 20 ALC Control Registers When the ALC is disabled, the input PGA remains at the last controlled value of the ALC. An input gain update must be made by writing to the INPPGAVOLL/R register bits. If there is no analogue input signal present when the ALC is enabled, the ALC may not function correctly. To ensure correct operation of the ALC with no analogue input signal, the Input PGA Volume control register (R45) should be written with the INPPGAMUTE and ALCZC bits set to 0 before setting the ALCSEL bit to 1 in register R32 (bit 8). NORMAL MODE In normal mode, the ALC will attempt to maintain a constant signal level by increasing or decreasing the gain of the PGA. The following diagram shows an example of this. Figure 12 ALC Normal Mode Operation |
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