WM9090ECSSLASHR datasheet(35/81 Pages) WOLFSON

35 / 81 page

Production Data

WM9090

PD, November 2010, Rev 4.1

The sequence of signals associated with a single register write operation is illustrated in Figure 7.

Figure 7 Control Interface Register Write

The sequence of signals associated with a single register read operation is illustrated in Figure 8.

SDA

SCLK

device ID

Note: The SDA pin is driven by both the master and slave devices in turn to transfer device address, register address, data and ACK responses

R/W

B15

data bits B15 – B8

START

(Write) ACK

ACK

R/W

(Read)

data bits B15 – B8

ACK

STOP

ACK

Rpt

START

Figure 8 Control Interface Register Read

The Control Interface also supports other register operations, as listed above. The interface protocol

for these operations is summarised below. The terminology used in the following figures is detailed in

Table 18.

Note that multiple write and multiple read operations are supported using the auto-increment mode.

This feature enables the host processor to access sequential blocks of the data in the WM9090

TERMINOLOGY

DESCRIPTION

Start Condition

Repeated start

Acknowledge (SDA Low)

¯ ¯

Not Acknowledge (SDA High)

Stop Condition

R/W

¯ ¯

ReadNotWrite

0 = Write

1 = Read

[White field]

Data flow from bus master to WM9090

[Grey field]

Data flow from WM9090 to bus master

Table 18 Control Interface Terminology

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