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ADL5303ACPZ-R7 bảng dữ liệu(PDF) 5 Page - Analog Devices |
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ADL5303ACPZ-R7 bảng dữ liệu(HTML) 5 Page - Analog Devices |
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5 / 24 page ![]() Data Sheet ADL5303 Rev. 0 | Page 5 of 24 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS PIN 1 INDICATOR NOTES 1. PINS LABELED NC CAN BE ALLOWED TO FLOAT, BUT IT IS BETTER TO CONNECT THESE PINS TO GROUND. AVOID ROUTING HIGH SPEED SIGNALS THROUGH THESE PINS BECAUSE NOISE COUPLING MAY RESULT. 2. EXPOSED PAD. CONNECT THE EXPOSED PAD TO THE VSUM PINS TO PROVIDE LOW LEAKAGE GUARD. 1 NC 2 VSUM 3 INPT 4 VSUM 11 VOUT 12 VPS1 10 VPS2 9 BFIN ADL5303 TOP VIEW (Not to Scale) Figure 2. Pin Configuration Table 3. Pin Function Descriptions Pin No. Mnemonic Description 1 NC Pins labeled NC can be allowed to float, but it is better to connect these pins to ground. Avoid routing high speed signals through these pins because noise coupling may result. 2, 4 VSUM Guard Pins. VSUM is used to shield the INPT current line. 3 INPT Photodiode Current Input. Connect this pin to the photodiode anode (the photo current flows toward INPT). 5 VPDB Photodiode Biaser Output. Connect this pin to the photodiode cathode when using adaptive bias control; otherwise, leave this pin floating. 6 VREF Voltage Reference Output of 2 V. 7 ACOM Analog Reference Ground. 8 VLOG Output of the Logarithmic Front-End Processor. ROUT = 5 kΩ to ground. 9 BFIN Buffer Amplifier Noninverting Input (High Impedance). 10 VPS2 Positive Supply, VPS (3.0 V to 5.5 V). 11 VOUT Buffer Output; Low Impedance. 12 VPS1 Positive Supply, VPS (3.0 V to 5.5 V). 13 BFNG Buffer Amplifier Inverting Input. 14, 15 GND Power Supply Ground Connection. 16 PWDN Power-Down Control Input. Device is active when PWDN is taken low. 17 EPAD Exposed Pad. Connect the exposed pad to the VSUM pins to provide low leakage guard. |
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