LIS2DH datasheet(13/50 Pages) STMICROELECTRONICS

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13 / 50 page

LIS2DH

Mechanical and electrical specifications

Doc ID 022516 Rev 1

13/49

2.4

Communication interface characteristics

2.4.1

SPI - serial peripheral interface

Subject to general operating conditions for Vdd and Top.

Figure 3.

SPI slave timing diagram(d)

When no communication is on-going, data on SDO is driven by internal pull-up resistors

Table 6.

SPI slave timing values

Symbol

Parameter

Value (1)

Unit

Min

Max

tc(SPC)

SPI clock cycle

100

fc(SPC)

SPI clock frequency

MHz

tsu(CS)

CS setup time

th(CS)

CS hold time

tsu(SI)

SDI input setup time

th(SI)

SDI input hold time

tv(SO)

SDO valid output time

th(SO)

SDO output hold time

tdis(SO)

SDO output disable time

Values are guaranteed at 10 MHz clock frequency for SPI with both 4 and 3 wires, based on characterization results, not

tested in production

Measurement points are done at 0.2·Vdd_IO and 0.8·Vdd_IO, for both Input and output port.

SPC

SDI

SDO

tsu(CS)

tv(SO)

th(SO)

th(SI)

tsu(SI)

th(CS)

tdis(SO)

tc(SPC)

MSB IN

MSB OUT

LSB OUT

LSB IN

(3)

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