T7121-PL2 datasheet(46/68 Pages) AGERE

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Lucent Technologies Inc.

Data Sheet

April 1997

T7121 HDLC Interface for ISDN (HIFI-64)

Clock Characteristics

System Clock Input (CLK): 0 MHz—12 MHz.

Transmit Data Clock (CLKX): no minimum frequency*, <CLK/2 maximum frequency to 4.096 MHz.

Receive Data Clock (CLKR): no minimum frequency*, <CLK/2 maximum frequency to 4.096 MHz.

* 8.192 MHz in CMS mode (R8—B6 = 1).

Timing Characteristics

TDM Frame Timing Diagrams

The timing of the transmission or reception of the ﬁrst bit relative to the frame-sync pulse depends on the conﬁgu-

ration of 3 bits: FE (R0—B5), CLKXI (R9—B4), CLKRI (R9—B0). The timing diagrams below illustrate different

conﬁgurations of FE, CLKXI, and CLKRI.

5-5038

Figure 12. FE = 0, CLKXI = 0, CLKRI = 0

234567

FRAME SYNC SAMPLED ON THIS EDGE OF CLKX/CLKR

FIRST BIT TRANSMITTED

CLKX/CLKR

(FE = 0)

DXA/B

(CLKXI = 0)

TSCA

DRA/B

(CLKRI = 0)

3-STATE

FIRST BIT SAMPLED

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