OR4E2 datasheet(42/124 Pages) AGERE

42 / 124 page

Lucent Technologies Inc.

Preliminary Data Sheet

December 2000

ORCA Series 4 FPGAs

Special Function Blocks (continued)

ORCA Boundary-Scan Circuitry

The ORCA Series boundary-scan circuitry includes a

test access port controller (TAPC), instruction register

(IR), boundary-scan register (BSR), and bypass regis-

ter. It also includes circuitry to support the 18 pre-

defined instructions.

Figure 27 shows a functional diagram of the boundary-

scan circuitry that is implemented in the ORCA Series.

The input pins’ (TMS, TCK, and TDI) locations vary

depending on the part, and the output pin is the dedi-

cated TDO/RD_DATA output pad. Test data in (TDI) is

the serial input data. Test mode select (TMS) controls

the boundary-scan TAPC. Test clock (TCK) is the test

clock on the board.

The BSR is a series connection of boundary-scan cells

(BSCs) around the periphery of the IC. Each I/O pad on

the FPGA, except for CCLK, DONE, and the boundary-

scan pins (TCK, TDI, TMS, and TDO), is included in

the BSR. The first BSC in the BSR (connected to TDI)

is located in the first PIO I/O pad on the left of the top

side of the FPGA (PTA PIO). The BSR proceeds clock-

wise around the top, right, bottom, and left sides of the

array. The last BSC in the BSR (connected to TDO) is

located on the top of the left side of the array (PL1D).

The bypass instruction uses a single FF, which resyn-

chronizes test data that is not part of the current scan

operation. In a bypass instruction, test data received on

TDI is shifted out of the bypass register to TDO. Since

the BSR (which requires a two FF delay for each pad)

is bypassed, test throughput is increased when devices

that are not part of a test operation are bypassed.

The boundary-scan logic is enabled before and during

configuration. After configuration, a configuration

option determines whether or not boundary-scan logic

is used.

The 32-bit boundary-scan identification register con-

tains the manufacturer’s ID number, unique part num-

ber, and version (as described earlier). The

identification register is the default source for data on

TDO after RESET if the TAP controller selects the shift-

data-register (SHIFT-DR) instruction. If boundary scan

is not used, TMS, TDI, and TCK become user I/Os, and

TDO is 3-stated or used in the readback operation.

An optional USERCODE is available. The USERCODE

is a 32-bit value that the user can set during device

configuration and can be written to and read from the

FPGA via the boundary-scan logic.

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