LCK4950 datasheet(13/16 Pages) AGERE

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Giải thích chi tiết về linh kiện	Low-Voltage PLL Clock Driver

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Agere Systems Inc.

Data Sheet

November 2001

Low-Voltage PLL Clock Driver

LCK4950

Electrical Characteristics (continued)

5-9708 (F)

Figure 9. PLL Block Diagram

Note: For computations refer to the following equations:

m = 8 (FBsel = 1), 16(FBsel = 0), P = 1

For the LCK4950 clock driver, the following will provide an example of how to determine the crystal frequency

required for a given design.

Given:

Qa = 160 MHz

Qb = 80 MHz

Qc = 40 MHz

Qd = 40 MHz

FBSel = 0

(eq. 1)

From Figure 3:

fQd = VCO/8 then N = 8 or fQa = VCO/2 then N = 2

From Figure 9:

m = 16 and P = 1

PHASE

DETECTOR

LPF

VCO

÷P

÷N

÷m

fref

fVCO

--------------

fvco

fref

fQn

•

------------------------------

∴

fref

fQn

•

------------------------------

tref

4081

•

------------------------

20 MHz

tref

16021

•

----------------------------

20 MHz

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