TLC5949 datasheet(39/51 Pages) TI

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Power-Save Mode

191

192

193

SIN

LAT

Second GS Data Latch

(Internal)

Previous On/Off Data

SCLK

All Data Are '0'

Low

Power-Save Mode

Normal Mode

'1'

PSMODE Bit

in Control Data Latch

(Internal)

X01b or X10b

OFF

OUT0,

OUT

OFF

OUT1,

OUT

OFF

ICC

(VCC Current)

Greater Than 1 mA

Approximately 10 A

BLANK Bit

in Control Data Latch

(Internal)

ON or OFF

OFF

OUT2,

10,

OUT

ON or OFF

OUT3,

11,

OUT

First GS Data Latch

(Internal)

Previous On/Off Data

All Data Are '0'

First and second GS data latches are

changed simultaneously because the BLANK bit is '1'.

TLC5949

www.ti.com

SBVS219A – DECEMBER 2012 – REVISED DECEMBER 2012

POWER-SAVE MODE (PSM)

The power-save mode control bits are assigned in the function control data latch. The device dissipation current

becomes 10 µA (typ) in this mode. When the two lower bits in PSMODE are '01', '10', or '11', the power-save

mode is enabled. When the lower two bits are '01' or '10', and if all '0' data are written in the second GS data

latch, the TLC5949 goes into power-save mode. When an SCLK rising edge is generated with the lower two

PSMODE bits (bits 135, 134) set to '01', the device leaves PSM for normal operation. OUTn are turned on at the

first GSCLK of the next display period after the device has left PSM. Figure 33 shows the power-save mode

timing diagram.

Figure 33. Power-Save Mode Timing (Bits 135 and 134 = 01)

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