SWRS126-005

VBAT_IN

VIO_HOST

VBAT_SW_EN

SPI_IRQ

SPI_CS

T0

T1

T2

CC3000MOD

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SWRS126 – NOVEMBER 2012

POWER-UP SEQUENCE

Figure 5 demonstrates the wake-up sequence of the CC3000 module.

Figure 5. CC3000 Module Power-On Sequences

NOTE

•

VBAT_IN and VIO_HOST must be available before VBAT_SW_EN is asserted.

•

At wake-up time (T1): The CC3000 module powers up after SPI_IRQ changes state to

LOW. T1 is approximately 53 ms.

•

At T2: The normal master SPI write sequence is SPI_CS low, followed by SPI_IRQ low

(CC3000 host), indicating that the CC3000 core module is ready to accept data. T2

duration is approximately 7 ms.

CC3000 Enable Pins Configuration

Table 5 describes the CC3000 mode of operation based on the enable (EN) pins setting.

Table 5. CC3000 EN Pins Configuration

Mode

State

WL_EN1: Leave disconnected.

WL_EN2: Connect to ground.

WL_EN1 and WL_EN2 are shorted together.

(1)

For CC3000 radio tool operation

(2)

For normal operation

Copyright © 2012, Texas Instruments Incorporated

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