PIN A1

IDENTIFIER

A

B

C

D

1

2

3

4

VDD

VIO

SCLK

SDATA

VDDIO

GND

ADR

GPO_0

GPO_6

GPO_7

CFG

GPO_1

GPO_5

GPO_4

GPO_3

GPO_2

Top View

LM8335

SNVS840 – JUNE 2012

www.ti.com

Connection Diagram and Package Mark Information

Note: This is a preliminary pinout (pin sequence not fixed)

Figure 1. 16-Bump DSBGA Pinout

1.965mm x 1.965mm x 0.6mm (nom), 0.5mm pitch

See Package Number YZR0016

Figure 2. A1 Pin Identifier

PIN DESCRIPTIONS

Pin Number

Name

Description

8

GPO_0 through GPO_7

General purpose outputs

1

SCLK

RFFE clock input

1

SDATA

RFFE data input

RFFE chip address input

1

ADR

ADR = VDD: USID[3:0] = b1001

ADR = GND: USID[3:0] = b0001

Initial configuration select

CFG = VDD: GPO high-z with weak internal pull-down resistor enabled,

1

CFG

GPO_OUT_DATA masked

CFG = GND: GPO high-z, with weak internal pull-down resistor enabled,

GPO_OUT_DATA unmasked

1

VIO

MIPI RFFE VIO (1.8V ± 0.15V)

1

VDD

Core supply VDD (1.8V ± 0.15V)

1

VDDIO

GPO supply VDDIO (1.65V to 3.6V)

1

GND

Ground

4

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