DAC312 datasheet(4/14 Pages) AD

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DAC312

–4–

REV. C

WAFER TEST LIMITS

DAC312N

DAC312G

Parameter

Symbol

Conditions

Limit

Units

Resolution

Bits min

Monotonicity

Bits min

Nonlinearity

±0.05

%FS max

Output Voltage

Full-Scale Current

+10

V max

Compliance

Voc

Change <1/2 LSB

–5

V min

Full-Scale

VREF = 10.000 V

4.031

4.063

mA max

Current

R14, R15 = 10.000 kΩ

3.967

3.935

mA min

Full-Scale Symmetry

IFSS

±1

±2

µA max

Zero-Scale Current

IZS

0.1

µA max

Differential

DNL

Deviation from

±0.012

±0.025

%FS max

Nonlinearity

Ideal Step Size

±1/2

±1

Bits (LSB) max

Logic Input Levels “0”

VIL

VLC = GND

0.8

V max

Logic Input Levels “1”

VIH

VLC = GND

V min

Logic Input Swing

VIS

+18

V max

–5

V min

Reference Bias

Current

I15

–2

µA max

Power Supply

PSSIFS+

V+ = +13.5 V to +16.5 V, V– = –15 V

±0.001

Sensitivity

PSSIFS–

V– = –13.5 V to –16.5 V, V+ = +15 V

±0.001

%/%max

Power Supply

I+

VS = +15 V

Current

I–

IREF ≤ 1.0 mA

–18

mA max

Power

VS = +15 V

Dissipation

IREF ≤ 1.0 mA

375

mW max

NOTE

Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed

for standard product dice. Consult factory to negotiate specifications based on dice lot qualification through sample lot assembly and testing.

@ VS =

15 V, IREF = 1.0 mA, TA = 25 C, unless otherwise noted. Output characteristics refer to both IOUT and IOUT.

DICE CHARACTERISTICS

DIE SIZE 0.141

× 0.096 inch, 13,536 sq. mils (3.58 × 2.44 mm, 8.74 sq. mm)

1. B1 (MSB)

11. B11

2. B2

12. B12 (LSB)

3. B3

13. VLC/AGND

4. B4

14. VREF(+)

5. B5

15. VREF(–)

6. B6

16. COMP

7. B7

17. V–

8. B8

18. IO

9. B9

19. IO

10. B10

20. V+

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