ADV7150

–5–

REV. A

PIXEL INPUT

DATA*

A

C

CLOCK

LOADOUT

LOADIN

ANALOG

OUTPUT

DATA

t

10

t

PD

DIGITAL

INPUT

TO ANALOG

OUTPUT

PIPELINE

A

C

*INCLUDES PIXEL DATA (R0–R7, G0–G7, B0–B7); PALETTE SELECT INPUTS (PS0–PS1); BLANK; SYNC

A

C

A

N

B

N

C

N

D

N

A

N+1

B

N+1

C

N+1

D

N+1

A

N–1

B

N–1

C

N–1

D

N–1

A

N+2

B

N+2

C

N+2

D

N+2

IOR, IOR

IOG, IOG

IOB, IOB

IPLL, SYNCOUT

Figure 4. Pixel Input to Analog Output Pipeline with Minimum LOADOUT to LOADIN Delay (4:1 Multiplex Mode)

DIGITAL

INPUT

TO

ANALOG

OUTPUT

PIPELINE

A

C

CLOCK

LOADOUT

PIXEL INPUT

DATA*

LOADIN

ANALOG

OUTPUT

DATA

A

N

B

N

C

N

D

N

A

C

A

N+1

B

N+1

C

N+1

D

N+1

A

N–1

B

N–1

C

N–1

D

N–1

A

N+2

B

N+2

C

N+2

D

N+2

t

PD

τ

τ– t

11

*INCLUDES PIXEL DATA (R0–R7, G0–G7, B0–B7); PALETTE SELECT INPUTS (PS0–PS1); BLANK; SYNC

IOR, IOR

IOG, IOG

IOB, IOB

IPLL, SYNCOUT

A

C

Figure 5. Pixel Input to Analog Output Pipeline with Maximum LOADOUT to LOADIN Delay (4:1 Multiplex Mode)