REV. A

ADP3162

–9–

R

V

VV

R

gV

V

R

V

VV

k

mmho

mV

k

B

REF

REF

GNL

T

m

ONL

OUT

B

=

−

−×

−

=

−

Ω

−×

=Ω

()

.

.

.

.

3

3

1 194

71

22

45

19 31

(11)

Ω. Finally,

R

RR

R

k

k

k

k

A

T

OGM

B

=

−−

=

Ω

−

Ω

−

Ω

=Ω

1

11

1

1

1

71

1

200

1

19 1

11 98

..

.

(12)

Ω.

The required equivalent series resistance (ESR) and capacitance

drive the selection of the type and quantity of the output capaci-

tors. The ESR of the output filter capacitor bank must be equal

to or less than the specified output resistance (3.2 m

Ω) of the

voltage regulator. The capacitance must be large enough that

the voltage across the capacitor, which is the sum of the resistive

and capacitive voltage drops, does not moves below or above the

initial resistive step while the inductor current ramps up or

down to the value corresponding to the new load current.

One can use, for example, four SP-Type OS-CON capacitors

from Sanyo, with 820

µF capacitance, a 4 V voltage rating,

and 12 m

Ω ESR. The four capacitors have a maximum total

ESR of 3 m

Ω when connected in parallel. Another possibility is

the ZA series from Rubycon. The trade-off is size versus cost.

Eight 1000

µF capacitors would give an ESR of 3 mΩ. These

eight capacitors take up more space than four OS-CON capaci-

tors, but are significantly less expensive.

As long as the capacitance of the output capacitor is above a

critical value and the regulating loop is compensated with

Analog Devices’ proprietary compensation technique, ADOPT,

the actual value has no influence on the peak-to-peak deviation

of the output voltage to a full step change in the load current.

The critical capacitance can be calculated as follows:

C

I

RV

L

A

mV

H

mF

OUT CRIT

O

OUT

OFL

()

..

.

=

×

×

×

× µ

=

2

28

32

1755

1

2

249

Ω

(13)

The equivalent capacitance of the four OS-CON capacitors is

4

× 820 µF = 3.28 mF, and the equivalent capacitance of the

eight ZA series Rubycon capacitors is 8 mF. With both choices,

the total capacitance is safely above the critical value.

Feedback Loop Compensation Design for ADOPT

Optimized compensation of the ADP3162 allows the best pos-

sible containment of the peak-to-peak output voltage deviation.

The output current slew rate of any practical switching power

converter is inherently limited by the inductor to a value much

less than the slew rate of the load. Therefore, any sudden change of

load current will initially flow through the output capacitors,

and assuming that the capacitance of the output capacitor is

larger than the critical value defined by Equation 14, this will

produce a peak output voltage deviation equal to the ESR of the

output capacitor times the load current change.

The optimal implementation of voltage positioning, ADOPT,

will create an output impedance of the power converter that is

entirely resistive over the widest possible frequency range—

including dc—and equal to the specified dc output resistance.

With the wide-band resistive output impedance the output

voltage will droop in proportion with the load current at any

load current slew rate; this ensures the optimal positioning and

allows the minimization of the output capacitor.

With an ideal current-mode controlled converter, where the

inductor current would respond without delay to the command

signal, the resistive output impedance could be achieved by having

a single-pole roll-off of the voltage gain of the voltage-error

amplifier. The pole frequency must coincide with the ESR zero

of the output capacitor. The ADP3162 uses constant-frequency

peak-current control, which is known to have a nonideal, frequency

dependent command-signal-to-inductor-current transfer func-

tion. The frequency dependence manifests in the form of a pair

of complex conjugate poles at one-half of the switching frequency.

A purely resistive output impedance could be achieved by can-

celing the complex conjugate with zeros at the same complex

frequencies and adding a third pole equal to the ESR zero of the

output capacitor. Such a compensating network would be quite

complicated. Fortunately, in practice it is sufficient to cancel the

pair of complex conjugate poles with a single real zero placed at

one-half of the switching frequency. Although the end result is

not a perfectly resistive output impedance, the remaining fre-

quency dependence causes only a few percentage of deviation

from the ideal resistive response. The single-pole and single-zero

and a series RC network. The value of the terminating resistor

the series RC network are calculated as follows:

C

CR

Rf

R

OC

OUT

OUT

T

OSC

T

=

×

−

××

2

π

(14)

For the Rubycon output capacitors, the compensating capaci-

tor is:

C

mF

m

k

kHz

k

nF

×Ω

Ω

−

××

Ω

=

83

71

2

400

7 1

316

..

.

π

The closest standard value is 3.3 nF.

R

C

f

nF

kHz

Z

OC

OSC

=

××

=

××

=Ω

22

3 3

400

483

ππ

.

(15)

The nearest standard 5% resistor value is 470

Ω. Note that this

fore be omitted.

Power MOSFETs

In the standard two-phase application two pairs of N-channel

power MOSFETs must be used with the ADP3162 and ADP3412,

one pair as the main (control) switches, and the other pair as

the synchronous rectifier switches. The main selection parameters

mum gate drive voltage (the supply voltage to the ADP3412)