ADMC401 datasheet(6/60 Pages) AD

tên linh kiện	ADMC401

Giải thích chi tiết về linh kiện	Single-Chip, DSP-Based High Performance Motor Controller

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REV. B

ADMC401

–6–

Parameter

Min

Max

Unit

Interrupts and Flags

Timing Requirements:

IFS

IRQx or FI Setup before CLKOUT Low1, 2, 3

0.25t

CK + 15

IFH

IRQx or FI Hold after CLKOUT High1, 2, 3

0.25t

Switching Characteristics:

FOH

Flag Output Hold after CLKOUT Low

0.5t

CK – 7

FOD

Flag Output Delay from CLKOUT Low

0.5t

CK + 5

NOTES

1If

IRQx and FI inputs meet t

IFS and tIFH setup/hold requirements, they will be recognized during the current clock cycle; otherwise the signals will be recognized on

the following cycle. (Refer to “Interrupt Controller Operation” in the Program Control chapter of the ADSP-2100 Family User’s Manual, Third Edition for further

information on interrupt servicing.)

2Edge-sensitive interrupts require pulsewidths greater than 10 ns; level-sensitive interrupts must be held low until serviced.

IRQx = IRQ0 and IRQ1.

4Flag Output = FL1 and FO.

CLKOUT

FLAG

OUTPUTS

IRQx

tFOH

tIFH

tIFS

tFOD

Figure 2. Interrupts and Flags

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